library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Braun_8x8 is
PORT (A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
P : out STD_LOGIC_VECTOR (15 downto 0));

end Braun_8x8;

architecture Behavioral of Braun_8x8 is

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signal A1B0 : STD_LOGIC;
signal A2B0 : STD_LOGIC;
signal A3B0 : STD_LOGIC;
signal A4B0 : STD_LOGIC;
signal A5B0 : STD_LOGIC;
signal A6B0 : STD_LOGIC;
signal A7B0 : STD_LOGIC;

signal A0B1 : STD_LOGIC;
signal A1B1 : STD_LOGIC;
signal A2B1 : STD_LOGIC;
signal A3B1 : STD_LOGIC;
signal A4B1 : STD_LOGIC;
signal A5B1 : STD_LOGIC;
signal A6B1 : STD_LOGIC;
signal A7B1 : STD_LOGIC;

signal A0B2 : STD_LOGIC;
signal A1B2 : STD_LOGIC;
signal A2B2 : STD_LOGIC;
signal A3B2 : STD_LOGIC;
signal A4B2 : STD_LOGIC;
signal A5B2 : STD_LOGIC;
signal A6B2 : STD_LOGIC;
signal A7B2 : STD_LOGIC;

signal A0B3 : STD_LOGIC;
signal A1B3 : STD_LOGIC;
signal A2B3 : STD_LOGIC;
signal A3B3 : STD_LOGIC;
signal A4B3 : STD_LOGIC;
signal A5B3 : STD_LOGIC;
signal A6B3 : STD_LOGIC;
signal A7B3 : STD_LOGIC;

signal A0B4 : STD_LOGIC;
signal A1B4 : STD_LOGIC;
signal A2B4 : STD_LOGIC;
signal A3B4 : STD_LOGIC;
signal A4B4 : STD_LOGIC;
signal A5B4 : STD_LOGIC;
signal A6B4 : STD_LOGIC;
signal A7B4 : STD_LOGIC;

signal A0B5 : STD_LOGIC;
signal A1B5 : STD_LOGIC;
signal A2B5 : STD_LOGIC;
signal A3B5 : STD_LOGIC;
signal A4B5 : STD_LOGIC;
signal A5B5 : STD_LOGIC;
signal A6B5 : STD_LOGIC;
signal A7B5 : STD_LOGIC;

signal A0B6 : STD_LOGIC;
signal A1B6 : STD_LOGIC;
signal A2B6 : STD_LOGIC;
signal A3B6 : STD_LOGIC;
signal A4B6 : STD_LOGIC;
signal A5B6 : STD_LOGIC;
signal A6B6 : STD_LOGIC;
signal A7B6 : STD_LOGIC;

signal A0B7 : STD_LOGIC;
signal A1B7 : STD_LOGIC;
signal A2B7 : STD_LOGIC;
signal A3B7 : STD_LOGIC;
signal A4B7 : STD_LOGIC;
signal A5B7 : STD_LOGIC;
signal A6B7 : STD_LOGIC;
signal A7B7 : STD_LOGIC;

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

signal C1    : STD_LOGIC;

signal C2    : STD_LOGIC;
signal C2_1  : STD_LOGIC;

signal C3    : STD_LOGIC;
signal C3_1  : STD_LOGIC;
signal C3_2  : STD_LOGIC;

signal C4    : STD_LOGIC;
signal C4_1  : STD_LOGIC;
signal C4_2  : STD_LOGIC;
signal C4_3  : STD_LOGIC;

signal C5    : STD_LOGIC;
signal C5_1  : STD_LOGIC;
signal C5_2  : STD_LOGIC;
signal C5_3  : STD_LOGIC;
signal C5_4  : STD_LOGIC;

signal C6    : STD_LOGIC;
signal C6_1  : STD_LOGIC;
signal C6_2  : STD_LOGIC;
signal C6_3  : STD_LOGIC;
signal C6_4  : STD_LOGIC;
signal C6_5  : STD_LOGIC;

signal C7    : STD_LOGIC;
signal C7_1  : STD_LOGIC;
signal C7_2  : STD_LOGIC;
signal C7_3  : STD_LOGIC;
signal C7_4  : STD_LOGIC;
signal C7_5  : STD_LOGIC;
signal C7_6  : STD_LOGIC;

signal C8    : STD_LOGIC;
signal C8_1  : STD_LOGIC;
signal C8_2  : STD_LOGIC;
signal C8_3  : STD_LOGIC;
signal C8_4  : STD_LOGIC;
signal C8_5  : STD_LOGIC;
signal C8_6  : STD_LOGIC;

signal C9    : STD_LOGIC;
signal C9_1  : STD_LOGIC;
signal C9_2  : STD_LOGIC;
signal C9_3  : STD_LOGIC;
signal C9_4  : STD_LOGIC;
signal C9_5  : STD_LOGIC;

signal C10    : STD_LOGIC;
signal C10_1  : STD_LOGIC;
signal C10_2  : STD_LOGIC;
signal C10_3  : STD_LOGIC;
signal C10_4  : STD_LOGIC;

signal C11    : STD_LOGIC;
signal C11_1  : STD_LOGIC;
signal C11_2  : STD_LOGIC;
signal C11_3  : STD_LOGIC;

signal C12    : STD_LOGIC;
signal C12_1  : STD_LOGIC;
signal C12_2  : STD_LOGIC;

signal C13    : STD_LOGIC;
signal C13_1  : STD_LOGIC;

signal C14    : STD_LOGIC;


signal P2_1  : STD_LOGIC;

signal P3_1  : STD_LOGIC;
signal P3_2  : STD_LOGIC;

signal P4_1  : STD_LOGIC;
signal P4_2  : STD_LOGIC;
signal P4_3  : STD_LOGIC;

signal P5_1  : STD_LOGIC;
signal P5_2  : STD_LOGIC;
signal P5_3  : STD_LOGIC;
signal P5_4  : STD_LOGIC;

signal P6_1  : STD_LOGIC;
signal P6_2  : STD_LOGIC;
signal P6_3  : STD_LOGIC;
signal P6_4  : STD_LOGIC;
signal P6_5  : STD_LOGIC;

signal P7_1  : STD_LOGIC;
signal P7_2  : STD_LOGIC;
signal P7_3  : STD_LOGIC;
signal P7_4  : STD_LOGIC;
signal P7_5  : STD_LOGIC;
signal P7_6  : STD_LOGIC;

signal P8_1  : STD_LOGIC;
signal P8_2  : STD_LOGIC;
signal P8_3  : STD_LOGIC;
signal P8_4  : STD_LOGIC;
signal P8_5  : STD_LOGIC;
signal P8_6  : STD_LOGIC;

signal P9_1  : STD_LOGIC;
signal P9_2  : STD_LOGIC;
signal P9_3  : STD_LOGIC;
signal P9_4  : STD_LOGIC;
signal P9_5  : STD_LOGIC;

signal P10_1  : STD_LOGIC;
signal P10_2  : STD_LOGIC;
signal P10_3  : STD_LOGIC;
signal P10_4  : STD_LOGIC;

signal P11_1  : STD_LOGIC;
signal P11_2  : STD_LOGIC;
signal P11_3  : STD_LOGIC;

signal P12_1  : STD_LOGIC;
signal P12_2  : STD_LOGIC;

signal P13_1  : STD_LOGIC;

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Component full_adder 
port (A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;

Component half_adder 
port (A : in STD_LOGIC;
B : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

begin

A1B0 <= A (1) AND B (0); 
A2B0 <= A (2) AND B (0); 
A3B0 <= A (3) AND B (0); 
A4B0 <= A (4) AND B (0); 
A5B0 <= A (5) AND B (0); 
A6B0 <= A (6) AND B (0); 
A7B0 <= A (7) AND B (0); 

A0B1 <= A (0) AND B (1); 
A1B1 <= A (1) AND B (1);
A2B1 <= A (2) AND B (1);
A3B1 <= A (3) AND B (1);
A4B1 <= A (4) AND B (1);
A5B1 <= A (5) AND B (1);
A6B1 <= A (6) AND B (1);
A7B1 <= A (7) AND B (1);

A0B2 <= A (0) AND B (2);
A1B2 <= A (1) AND B (2);
A2B2 <= A (2) AND B (2);
A3B2 <= A (3) AND B (2);
A4B2 <= A (4) AND B (2);
A5B2 <= A (5) AND B (2);
A6B2 <= A (6) AND B (2);
A7B2 <= A (7) AND B (2);

A0B3 <= A (0) AND B (3); 
A1B3 <= A (1) AND B (3); 
A2B3 <= A (2) AND B (3); 
A3B3 <= A (3) AND B (3); 
A4B3 <= A (4) AND B (3); 
A5B3 <= A (5) AND B (3); 
A6B3 <= A (6) AND B (3); 
A7B3 <= A (7) AND B (3); 

A0B4 <= A (0) AND B (4); 
A1B4 <= A (1) AND B (4); 
A2B4 <= A (2) AND B (4); 
A3B4 <= A (3) AND B (4); 
A4B4 <= A (4) AND B (4); 
A5B4 <= A (5) AND B (4); 
A6B4 <= A (6) AND B (4); 
A7B4 <= A (7) AND B (4); 

A0B5 <= A (0) AND B (5);  
A1B5 <= A (1) AND B (5);  
A2B5 <= A (2) AND B (5);  
A3B5 <= A (3) AND B (5);  
A4B5 <= A (4) AND B (5);  
A5B5 <= A (5) AND B (5);  
A6B5 <= A (6) AND B (5);  
A7B5 <= A (7) AND B (5);  

A0B6 <= A (0) AND B (6);  
A1B6 <= A (1) AND B (6);  
A2B6 <= A (2) AND B (6);  
A3B6 <= A (3) AND B (6);  
A4B6 <= A (4) AND B (6);  
A5B6 <= A (5) AND B (6);  
A6B6 <= A (6) AND B (6);  
A7B6 <= A (7) AND B (6);  

A0B7 <= A (0) AND B (7);
A1B7 <= A (1) AND B (7);
A2B7 <= A (2) AND B (7);
A3B7 <= A (3) AND B (7);
A4B7 <= A (4) AND B (7);
A5B7 <= A (5) AND B (7);
A6B7 <= A (6) AND B (7);
A7B7 <= A (7) AND B (7);

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

P0 : P(0) <= A(0) and B(0);

P1_0 : half_adder port map (A=>A1B0 , B=>A0B1 ,S=> P(1), Cout=>C1);

P21 : full_adder port map (A=>A2B0 , B=>A1B1 , Cin=>C1, S=>P2_1, Cout=>C2_1);
P2_0 : half_adder port map (A=>A0B2 , B=>P2_1 , S=>P(2), Cout=>C2);

P31 : full_adder port map (A=>A3B0 , B=>A2B1, Cin=>C2_1, S=>P3_1, Cout=>C3_1);
P32 : full_adder port map (A=>A1B2, B=>P3_1 , Cin=>C2, S=>P3_2, Cout=>C3_2);
P3_0 : half_adder port map (A=>A0B3, B=>P3_2, S=>P(3),Cout=>C3);

P41 : full_adder port map (A=>A4B0 , B=>A3B1, Cin=>C3_1, S=>P4_1, Cout=>C4_1);
P42 : full_adder port map (A=>A2B2, B=>P4_1 , Cin=>C3_2, S=>P4_2, Cout=>C4_2);
P43 : full_adder port map (A=>A1B3, B=>P4_2 , Cin=>C3, S=>P4_3, Cout=>C4_3);
P4_0 : half_adder port map (A=>A0B4, B=>P4_3, S=>P(4),Cout=>C4);

P51 : full_adder port map (A=>A5B0 , B=>A4B1, Cin=>C4_1, S=>P5_1, Cout=>C5_1);
P52 : full_adder port map (A=>A3B2, B=>P5_1 , Cin=>C4_2, S=>P5_2, Cout=>C5_2);
P53 : full_adder port map (A=>A2B3, B=>P5_2 , Cin=>C4_3, S=>P5_3, Cout=>C5_3);
P54 : full_adder port map (A=>A1B4, B=>P5_3 , Cin=>C4, S=>P5_4, Cout=>C5_4);
P5_0 : half_adder port map (A=>A0B5, B=>P5_4, S=>P(5),Cout=>C5);

P61 : full_adder port map (A=>A6B0 , B=>A5B1, Cin=>C5_1, S=>P6_1, Cout=>C6_1);
P62 : full_adder port map (A=>A4B2, B=>P6_1 , Cin=>C5_2, S=>P6_2, Cout=>C6_2);
P63 : full_adder port map (A=>A3B3, B=>P6_2 , Cin=>C5_3, S=>P6_3, Cout=>C6_3);
P64 : full_adder port map (A=>A2B4, B=>P6_3 , Cin=>C5_4, S=>P6_4, Cout=>C6_4);
P65 : full_adder port map (A=>A1B5, B=>P6_4 , Cin=>C5, S=>P6_5, Cout=>C6_5);
P6_0 : half_adder port map (A=>A0B6, B=>P6_5, S=>P(6),Cout=>C6);

P71 : full_adder port map (A=>A7B0 , B=>A6B1, Cin=>C6_1, S=>P7_1, Cout=>C7_1);
P72 : full_adder port map (A=>A5B2, B=>P7_1 , Cin=>C6_2, S=>P7_2, Cout=>C7_2);
P73 : full_adder port map (A=>A4B3, B=>P7_2 , Cin=>C6_3, S=>P7_3, Cout=>C7_3);
P74 : full_adder port map (A=>A3B4, B=>P7_3 , Cin=>C6_4, S=>P7_4, Cout=>C7_4);
P75 : full_adder port map (A=>A2B5, B=>P7_4 , Cin=>C6_5, S=>P7_5, Cout=>C7_5);
P76 : full_adder port map (A=>A1B6, B=>P7_5 , Cin=>C6, S=>P7_6, Cout=>C7_6);
P7_0 : half_adder port map (A=>A0B7, B=>P7_6, S=>P(7),Cout=>C7);

P81 : half_adder port map (A=>A7B1 , B=>C7_1, S=>P8_1, Cout=>C8_1);
P82 : full_adder port map (A=>A6B2, B=>P8_1 , Cin=>C7_2, S=>P8_2, Cout=>C8_2);
P83 : full_adder port map (A=>A5B3, B=>P8_2 , Cin=>C7_3, S=>P8_3, Cout=>C8_3);
P84 : full_adder port map (A=>A4B4, B=>P8_3 , Cin=>C7_4, S=>P8_4, Cout=>C8_4);
P85 : full_adder port map (A=>A3B5, B=>P8_4 , Cin=>C7_5, S=>P8_5, Cout=>C8_5);
P86 : full_adder port map (A=>A2B6, B=>P8_5 , Cin=>C7_6, S=>P8_6, Cout=>C8_6);
P8_0 : full_adder port map (A=>A1B7, B=>P8_6, Cin=>C7, S=>P(8), Cout=>C8);

P91 : full_adder port map (A=>C8_1, B=>A7B2 , Cin=>C8_2, S=>P9_1, Cout=>C9_1);
P92 : full_adder port map (A=>A6B3, B=>P9_1 , Cin=>C8_3, S=>P9_2, Cout=>C9_2);
P93 : full_adder port map (A=>A5B4, B=>P9_2 , Cin=>C8_4, S=>P9_3, Cout=>C9_3);
P94 : full_adder port map (A=>A4B5, B=>P9_3 , Cin=>C8_5, S=>P9_4, Cout=>C9_4);
P95 : full_adder port map (A=>A3B6, B=>P9_4 , Cin=>C8_6, S=>P9_5, Cout=>C9_5);
P9_0 : full_adder port map (A=>A2B7, B=>P9_5, Cin=>C8, S=>P(9), Cout=>C9);

P101 : full_adder port map (A=>C9_1, B=>A7B3 , Cin=>C9_2, S=>P10_1, Cout=>C10_1);
P102 : full_adder port map (A=>A6B4, B=>P10_1 , Cin=>C9_3, S=>P10_2, Cout=>C10_2);
P103 : full_adder port map (A=>A5B5, B=>P10_2 , Cin=>C9_4, S=>P10_3, Cout=>C10_3);
P104 : full_adder port map (A=>A4B6, B=>P10_3 , Cin=>C9_5, S=>P10_4, Cout=>C10_4);
P10_0 : full_adder port map (A=>A3B7, B=>P10_4, Cin=>C9, S=>P(10), Cout=>C10);

P111 : full_adder port map (A=>C10_1, B=>A7B4 , Cin=>C10_2, S=>P11_1, Cout=>C11_1);
P112 : full_adder port map (A=>A6B5, B=>P11_1 , Cin=>C10_3, S=>P11_2, Cout=>C11_2);
P113 : full_adder port map (A=>A5B6, B=>P11_2 , Cin=>C10_4, S=>P11_3, Cout=>C11_3);
P11_0 : full_adder port map (A=>A4B7, B=>P11_3, Cin=>C10, S=>P(11), Cout=>C11);

P121 : full_adder port map (A=>C11_1, B=>A7B5 , Cin=>C11_2, S=>P12_1, Cout=>C12_1);
P122 : full_adder port map (A=>A6B6, B=>P12_1 , Cin=>C11_3, S=>P12_2, Cout=>C12_2);
P12_0 : full_adder port map (A=>A5B7, B=>P12_2, Cin=>C11, S=>P(12), Cout=>C12);

P131 : full_adder port map (A=>C12_1 , B=>A7B6, Cin=>C12_2, S=>P13_1, Cout=>C13_1);
P13_0 : full_adder port map (A=>A6B7 , B=>P13_1, Cin=>C12, S=>P(13), Cout=>C13);

P14 : full_adder port map (A=>A7B7 , B=>C13_1, Cin=>C13, S=>P(14), Cout=> C14);
P15: P(15) <= C14;

end Behavioral;
